IOLTS 2005: Advanced Technical Program

ADVANCED TECHNICAL PROGRAM

Introduction --Technical Program -- General Information -- Committees

Introduction

Issues related to on-line testing are increasingly important in modern electronics systems. In particular, the huge complexity of electronic systems has seen reliability needs growing up in various application domains as well as pressure for low cost products. There is a corresponding increasing demand for cost-effective on-line testing techniques. These needs have increased dramatically with the introduction of very deep submicron and nanometer technologies. Nanometer technologies impact adversely noise margins and make mandatory integrating on-line test in modern ICs. The Symposium is also emphasizing on on-line testing in the continuous operation of large applications such as wired, cellular and satellite telecommunication, as well as in cryptographic chips.

The Symposium is sponsored by the IEEE Computer Society Test Technology Technical Council (TTTC), and co-organized by the TTTC On-line Testing TAC and the European Group of TTTC, in collaboration with TIMA Laboratory, University of Bologna, Purdue University, and IRoC Technologies.

Technical Program

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Wednesday July 6th, 2005
07.30 - 08.30	Registration
08.30 - 08.45	Welcome Message: General Co-Chairs: L. Anghel, M. Nicolaidis Program Co-Chairs: C. Metra, K. Roy
08.45 – 09.30	Keynote Session
09.30 - 09.45	Break
09.45 - 10.45	Session 1. Transient Fault Modeling and Analysis Moderators: N. Seifert, Intel Corporation; V. Chalendar, TI, Sofia Antipolis 1.1. "Analytical Semi-empirical Model for SER Sensitivity Estimation of Deep-Submicron CMOS Circuits," Tino Heijmen (Philips Research Laboratories) 1.2. "Electrical Modeling for Laser Testing with Different Pulse Durations," A. Douin, V. Pouget, D. Lewis, P. Fouillat, P. Perdu ( IXL Laboratory, CNES) 1.3. "Analysing the Effectiveness of Fault Handling Procedures," P. Gawkowski, J. Sosnowski, B. Radko (Warsaw University of Technology)
10.45 - 11.00	Break
11.00 - 12.00	Session 2. Transient Faults' Hardening Techniques Moderators: J. Hayes, University of Michigan; A. Salsano, University of Tor Vergata, Roma 2.1. "On Transistor Level Gate Sizing for Increased Robustness to Transient Faults," J. M. Cazeaux, D. Rossi, M. Omana, C. Metra (University of Bologna), Abhijit Chatterjee (Georgia Institute of Technology) 2.2. "On Implementing a Soft Error Hardening Technique by Using an Automatic Layout Generator: Case Study," Cristiano Lazzari (Universidade Federal do Rio Grande do Sul), Lorena Anghel (TIMA Laboratory), Ricardo A. L. Reis (Universidade Federal do Rio Grande do Sul) 2.3. "Output Load and Logic Co-Optimization for Design of Soft-Error Resistant Nanometer CMOS Circuits," Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee (Georgia Institute of Technology), Cecilia Metra (University of Bologna)
12.00 - 14.00	Lunch
14.00 - 15.00	Session 3. SEU Effects in FPGAs Moderators: P. Girard, LIRMM; M. Lubaszewski, UFRGS 3.1. "Autonomous Transient Fault Emulation on FPGAs for Accelerating Fault Grading," Celia López Ongil, Mario García Valderas, Marta Portela García, Luis Entrena Arrontes (University Carlos III of Madrid) 3.2. "Heavy Ion Effects on Configuration Logic of Virtex FPGAs," M. Alderighi, A. Candelori, F. Casini, S. D’Angelo, M. Mancini, A. Paccagnella, S. Pastore, G.R. Sechi, (Istituto di Astrofisica Spaziale e Fisica Cosmica, Istituto Nazionale di Fisica Nucleare, Sanitas EG and University of Padova) 3.3. "Efficient Estimation of SEU effects in SRAM-based FPGAs," M. Sonza Reorda, L. Sterpone, M. Violante (Politecnico di Torino)
15.00 - 15.15	Break
15.15 - 16.35	Special Session 1: Robust Design Techniques for Soft Errors Organizer: C. Metra, University of Bologna Moderator: C. Metra, University of Bologna S1.1. "Impact of Soft Error Challenge on SoC Design," Y. Zorian, V. Vardanian (Virage Logic) S1.2. "DFT Assisted Built-In Soft Error Resilience," T. M. Mak, S. Mitra, M. Zhang (Intel Corporation) S1.3. "Modeling soft-error susceptibility for IP blocks," R. Aitken, D. Bradley (ARM) S1.4. "Trends and Tradeoffs in Designing Highly Robust Throughput Computing Oriented Chips and Servers," I. Parulkar, R. Cypher (Sun Microsystems)
16.35 – 17.35	Special Session 2: Simulation and Mitigation of Single Event Effects Organizer: L. Anghel, TIMA Laboratory S2.1. "Use of Nuclear Codes for Neutron Induced Nuclear Reactions in Microelectronics, " Frédéric WROBEL (LPES-CRESA) S2.2. "A Review of DASIE Family Code: Contribution to SEU/MBU Understanding," Guillaume Hubert et al. (EADS-CCR) S2.3. "Mitigation Techniques for Single Event Effects," Michael Nicolaidis (iRoC Technologies)
17.35 - 17.50	Break
17.50 - 18.50	Special Session 3: Self Calibrating Design Organizer: K. Roy, Purdue University S3.1. "Does it Mean Less Testing for Self Calibrating Design?" T. M. Mak (Intel Corporation) S3.2. "Self Calibrating Circuit Design for Variation Tolerant VLSI Systems," Chris H. Kim (University of Minnesota), Steven Hsu, Ram Krishnamurthy, Shekhar Borkar (Intel Corporation), and Kaushik Roy (Purdue University) S3.3. "On-Chip Self-Calibration of RF Circuits Using Specification Based Built-In Self-Test (S-BIST)," DongHoon Han, Sermet Akbay, Soumendu Bhattacharya, A. Chatterjee (Gerorgia Institute of Technology), William R. Eisenstadt (University of Florida)
20.00	Welcome Dinner
Thursday, July 7th, 2005
08.30 -09.50	Special Session 4: Secure Implementation Organizer: R. Leveugle, TIMA Laboratory Moderator: R. Leveugle, TIMA Laboratory S4.1. "Introduction to Fault Attacks on Smartcard," Antoine Lemarechal, (Oberthur Card Systems) S4.2. "Security Constraints in Integrated Circuits," Laurent Sourgen, (STMicroelectronics) S4.3. "Side-channel Issues for Designing Secure Hardware Implementations," Lejla Batina, Nele Mentens, Ingrid Verbauwhede (K.U.Leuven) S4.4. "Security Testing for Hardware Products: the Security Evaluations Practice," Alain Merle, Jessy Clediere, (CESTI LETI, CEA)
9.50-10.50	Session 4: On-Line Testing for Secure and Asynchronous Chips Moderators: E. Simeu, Tima Laboratory; A. Pagni, STMicroelectronics 4.1. "Hardening Techniques against Transient Faults for Asynchronous Circuits," Y. Monnet, M. Renaudin, R. Leveugle (TIMA Laboratory) 4.2. "On-line Testing of Globally Asynchronous Circuits," D. Shang, A. Bystrov, A. Yakovlev, D. Koppad (University of Newcastle upon Tyne) 4.3. "On-Line Error Detection and BIST for the AES Encryption Algorithm with Different S-box Implementations," V. Ocheretnij, G. Kouznetsov (University of Potsdam), R. Karri (Polytechnic University), M. Goessel (University of Potsdam)
10.50 - 11.00	Break
11.00 - 12.00	Session 5. Self Checking Strategies Moderator: R. Stefanelli, Politecnico di Milano 5.1. "Fast, Parallel Two-Rail Code Checker with Enhanced Testability," S. Matakias, Y. Tsiatouhas, Th. Haniotakis, A. Arapoyanni, A. Efthymiou, (University of Athens), (University of Ioannia), (Southern Illinois University) 5.2. "Power-balanced Self Checking Circuits for Cryptographic Chips," J. Murphy, A. Bystrov, A. Yakovlev (University of Newcastle upon Tyne) 5.3. "On the Selection of Unidirectional Error Detecting Codes for Self-Checking Circuits' Area Overhead and Performance Optimization," M. Omaña, O. Losco, C. Metra (University of Bologna), A. Pagni (STMicroelectronics)
12.00 - 14.00	Lunch
14.00 - 15.00	Session 6. Process Variations, Leakage and Power Supply Noise Detection and Tolerance Moderator: C. Landrault, LIRMM; M. Pflanz, IBM 6.1. "Process Variation Tolerant Online Current Monitor for Fault Immune Systems," Q. Chen, S. Mukhopadhyay, H. Mahmoodi and K. Roy (Purdue University) 6.2. "A Non-Intrusive Built-In Sensor for Transient Current Testing of Digital VLSI Circuits," B. Alorda, S. Bota and J. Segura (Univ. de les Illes Balears) 6.3. "Coding Techniques for Low Switching Noise in Fault Tolerant Busses," A. K. Nieuwland, A. Katoch (Philips Research Laboratories), D. Rossi, C. Metra (University of Bologna)
15.00 – 15.40	Session 7. Posters Moderator: S. Hellebrand, University of Innsbruck 7.1. "Modeling of Transients Caused by a Laser Attack on Smart Cards," D. Leroy (iRoC Technologies), S. J. Piestrak, F. Monteiro, A. Dandache (University of Metz) 7.2. "Scrubbing and Partitioning for Protection of Memory Systems," R. Mariani, G. Boschi (Yogitech SPA) 7.3. "A Pragmatic Approach to Concurrent Error Detection in Sequential Circuits Implemented Using FPGAs with Embedded Memory," A. Krasniewski (Warsaw University of Technology) 7.4. "Software Based Online Memory Test for Highly Available Systems," A. Singh, D. Bose (Sun Microsystems) 7.5. "Design of a Self Checking Reed Solomon Encoder," Gian Carlo Cardarilli, S. Pontarelli, M. Re, A. Salsano (University of Rome ‚Tor Vergata‛) 7.6. "Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores using Reconfigurable Hardware and Scan Shift," K. Katoh (Chiba University), A. Doumar (Alakhawayn University), H. Ito (Chiba University) 7.7. "A 32-bit COTS-based Fault-Tolerant Embedded System," A. Rajabzadeh (Razi University) 7.8. "EMI-Based Fault Injection," Fabian Vargas, Danniel L. Cavalcante, Edmundo Gatti*, Da'rcio Prestes, Daniel Lupi, Eduardo Rhod, (Catholic University and Instituto Nacional de Tecnologia Industrial)
15.40 – 16.40	Panel: On-Line Testing for Secure Implementations: Design and Validation Organizer : R. Leveugle, Tima Laboratory Moderator : Y. Zorian, Virage Logic Participants: L. Breveglieri, Politecnico di Milano, Italy R. Leveugle, Tima Laboratory, France A. Nieuwland, Philips Research Labs., The Netherlands K. Rothbart, Tech. Univ. Graz, Austria J. P. Seifert, Intel Corporation, USA
17.30	Social Event (Tour and Gala Dinner)
Friday, July 8th, 2005
8.30 - 9. 30	Session 8: Testing Issues Moderator: B. Straube, Fraunhofer IIS/EAS; I. Polian, Albert-Ludwigs-Univ. of Freiburg 8.1. "Accumulator-based Weighted Pattern Generation," I. Voyiatzis, D. Gizopoulos, A. Paschalis, (TEI of Athens, University of Piraeus and University of Athens) 8.2. "A Hamming Distance Based Test Pattern Generator With Improved Fault Coverage," D. K. Pradhan (University of Bristol), D. Kagaris (Southern Illinois University) 8.3. "Test Generation Methodology for High-Speed Floating Point Adders," G. Xenoulis, M. Psarakis, D. Gizopoulos, A. Paschalis, (University of Piraeus and University of Athens)
09.30 - 10.30	Session 9. SoC Testing and Fault Tolerance Moderators: I. Levendel, Connectivities; E. Bohel, Robert Bosch GmbH 9.1. "Integrating BIST Techniques for On-line SoC Testing," A. Manzone, P. Bernardi, M. Grosso, M. Rebaudengo, E. Sanchez, M. Sonza Reorda (Centro Ricerche Fiat and Politecnico di Torino) 9.2. "A Multi-Purpose Concept for SoC Self Test Including Diagnostic Features," R. Kothe, C. Galke, H. T. Vierhaus (Brandenburg University of Technology) 9.3. "On the Need for Common Evaluation Methods for Fault Tolerance Costs in Microprocessors," M. Portolan, R. Leveugle (TIMA Laboratory)
10.30 - 10.45	Break
10.45 - 11. 45	Session 10. Multiple Bit Upset Evaluation and Correction Moderators: H-J. Wunderlich, Stuttgart University ; R. Velazco, Tima Laboratory 10.1. "Increasing Fault Tolerance to Multiple Upsets Using Digital Sigma-Delta Modulators," E. Schüler, L. Carro (Universidade Federal do Rio Grande do Sul) 10.2. "A New Approach for Early Dependability Evaluation Based on Formal Property Checking and Controlled Mutations," R. Leveugle (TIMA Laboratory) 10.3. "Radiation Induced Single-word Multiple-bit Upsets Correction in SRAM," B. Gill (Case Western Reserve University), M. Nicolaidis (iRoC Technologies), C. Papachristou (Case Western Reserve University)
11.45 - 12.45	Session 11: Timing, Yield, and Reliability Issues Moderator: A. Ivanov, University of Brit. Columbia 11.1. "Reliability Analysis and Yield Prediction of High Performance Pipelined Circuit with respect to Delay Failures in sub-100nm Technology," A. Datta, S. Mukhopadhyay, S. Bhunia, K. Roy (Purdue University) 11.2. "Dynamic Fault Test and Diagnosis in Digital Systems Using Multiple Clock Schemes and Multi-VDD Test," M. Rodriguez-Irago, J.J. Rodríguez Andina, F. Vargas, M. B. Santos, I.C Teixeira and J. P. Teixeira, (IST/INESC-ID, University of Vigo and PUCRS) 11.3. "A Novel On-chip Delay Measurement Hardware for Efficient Speed-Binning," A. Raychowdhury, S. Ghosh, K. Roy (Purdue University)
12.45 - 14.30	Lunch
14.30 – 16.50	Special Session 5: Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing Organizer: Y. Crouzet, LAAS-CNRS Moderator: J. Arlat, LAAS-CNRS S5.1. "Mitigating Soft Errors to Prevent a Hard Threat to Dependable Computing," Y. Crouzet, J. Collet, J. Arlat (LAAS-CNRS) S5.2. "Overview of Soft Errors Issues in Aerospace Systems," C. Boléat (Astrium EADS), G. Colas, (Thales Avionics) S5.3. "How to Characterize the Problem and Representative Errors Observed in Flight," R. Ecoffet ( CNES), R. Velazco, F. Faure (TIMA Laboratory) S5.4. "Evaluation of SET and SEU Effects at Multiple Abstraction Levels," L. Anghel, R. Leveugle, P. Vanhauwaert (TIMA Laboratory) S5.5. "How to Cope with SEU/SET at Chip Level? The Example of a Microprocessor Family," N. Renaud (ATMEL) S5.6. "How to Cope with SEU/SET at System Level?" M. Pignol (CNES) S5.7. "Strategic Use of SEE Mitigation Techniques for the Development of the ESA Microprocessor: Past, Present and Future," A. Pouponnot, (ESA/ESTE)
16.50 – 17.00	Closing

General Information

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About the location:
The On-Line Testing Symposium will be held in Mercure Hotel in Saint-Raphael, from July 6th through 8th. With 5 different harbors, the sailing resort of Saint-Raphael is the ideal place for boating enthusiasts.
Along its 42km. of coastline you can discover sandy beaches, creeks, and inlets, all carved out of the
famous red rock of the Esterel Mountains. Between the Mediterranean and calcareous Provence, the
Esterel Mountains are 32,000 ha. of volcanic rock of which 13,000 ha. are classified and protected.
This domain offers all kinds of sports including hiking, horseback riding, climbing, and mountain biking.
Saint-Raphael is also the city of Var where tourism and business are one. Originally a small fishing village,
Saint-Raphaël is now world-renowned for its huge choice of activities, wonderful climate, and beautiful environment. Saint-Raphaël comprises a delightful town centre plus a whole cluster of delightful and diverse quarters. Historic sites to see: the Church of the Templar Knights (11th and 12th c.), Notre Dame de Victoire Church, and the marine archeological museum.

Social Event:
This year the IOLTS Social Event will take place on Wednesday, July 6th and on Thursday, July 7th.
On Wednesday, July 6th, there is a Welcome Gala Dinner in Mercure Restaurant. On Thursday, July 7th, a boat trip takes all participants on a small cruise of the Saint Tropez bay. A special contest is organized during the welcome wine/local appetizers tasting on the famous Place de Lice of Saint Tropez.
The participants will enjoy a gastronomic dinner in one of the best restaurants in Saint Tropez.

Committees

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ORGANIZING COMMITTEE

General Chairs
M. Nicolaidis, iRoC Technologies
L. Anghel, TIMA Laboratory

Program Chairs
C. Metra, University of Bologna
K. Roy, Purdue University

Vice-General Chair
Y. Zorian, Virage Logic
D. Gizopoulos, University of Piraeus

Vice-Program Chair
R. Leveugle, TIMA Laboratory
J. P. Teixeira, IST/INESC-ID

Local Chair
R. Velazco, TIMA Laboratory

Publicity
D. Rossi, University of Bologna

Industrial Liaison
E. Dupont, iRoC Technologies

Publications
S. Bhunia, Purdue University

Audio Visual Chair
M. Portolan, TIMA Laboratory

ETTTC Liaison
J. Figueras, U. P. de Catalunya

PROGRAM COMMITTEE

M. Abadir, Freescale Semiconductor
J. Abraham, U. Texas at Austin
R. Aitken, ARM
R. Baumann, Texas Instruments
E. Boehl, Robert Bosch GmbH
C. Bolchini, Politec. Di Milano
S. Chakravarty, Intel Corporation
M. Cherif, Magma
A. Dandache, U. Metz
P. Fouillat, IXL-ENSEIRB
P. Girard, LIRMM
M. Goessel, U. of Postdam
T. Haniotakis, U. Southern Illinois
J. Hayes, U. of Michigan
T. Heijman, Philips Research Labs.
S. Hellebrand, U. of Innsbruck
A. Ivanov, U. of British. Columbia
R. Iyer, U. of Illinois
D. Kagaris, U. of Southern Illinois
B. Kaminska, Comet Micro
J. Karlsson, Chalmers U.
A. Krasniewski, Warsaw U. of Tec.
K. Kuchukyan, Armenian NAS
P. Lala, U. Arkansas
C. Landrault, LIRMM
I. Levendel, Connectivities
I. Levin, U. Tel Aviv
J. C. Lo, U. Rhode Island
Y. Makris, Yale U.
H. Manhaeve, Qstar
S. Mitra, Intel Corporation
A. Nieuwland, Philips Research Labs.
D. Nikolos, U. Patras
A. Orailoglu, U. Cal. San Diego
A. Paschalis, U. of Athens
M. Pflanz, IBM Germany
S. Piestrak, U. of Metz
D. Pradhan, U. Bristol
P. Prinetto, Politec. di Torino
M. Rebaudengo, Politec. di Torino
J. Segura, U. Illes Balears
N. Seifert, Intel Corporation
E. Simeu, TIMA Laboratory
M. Sonza Reorda, Politec. di Torino
J. Sosnowski, Warsaw U. of Tec.
G. Stamoulis, U. Crete
B. Straube, Fraunhofer IIS/EAS
N. Touba, U. Texas
S. Tragoudas, U. Southern Illinois
Y. Tsiatouhas, ISD
F. Vargas, PUCRS
H. T. Vierhaus, Brandenburg T. U.
M. Violante, Politec. di Torino
H. J. Wunderlich, U. of Stuttgart

For more information, visit us on the web at: http://tima.imag.fr/conferences/IOLTS/iolts05/Index.html

The 11th IEEE International On-Line Testing Symposium (IOLTS 05) is sponsored by the Institute of Electrical and Electronics Engineers (IEEE) Computer Society's Test Technology Technical Council (TTTC), and co-organized by the TTTC On-line Testing TAC and the European Group of TTTC, in collaboration with TIMA Laboratory, University of Bologna, Purdue University, and IRoC Technologies.